The performance of today's deep sub-micron semiconductor processes is becoming more dependent upon the parasitic capacitances of metal interconnects. The parasitic capacitances are formed due to the coupling between a metallic interconnect and a substrate or between pairs of metallic interconnects. In order to properly calibrate CAD tools which extract interconnect capacitances from completed layouts, test chips are often designed and fabricated with many test structures composed of accurately controlled interconnect geometries. When the capacitance of these various structures is measured on the actual silicon, they are compared with the extracted results to assess the degree of correlation. If discrepancies exist, the information is taken back to the vendor of the CAD tool whereby enhancements can be made to improve the extraction accuracy.
One of the conventional test structures has been described in a paper, “A Simple Method for On-Chip, Sub-Femto Farad Interconnect Capacitance Measurement” by McGaughy, Chen, Sylvester and Hu in the IEEE Electron Device Letters, Vol. 18, No. 1, January 1997. FIG. 1 is a block diagram of a test structure 100 described in the above mentioned paper which illustrates an example test structure design.
The test structure 100 consists of a pseudo-inverter driving the interconnect geometry which is a vertical Metal 2 line creating an overlap capacitance with the Metal 1 interconnect stub from the driver. The overlap capacitance is the desired measurement. It is called a pseudo-inverter because the P-channel gate and the N-channel gate do not receive the same signal. V1 and V2 are non-overlapping periodic waveforms as shown in FIG. 2.
The V1 positive-going pulse discharges the output net, and then the V2 negative-going pulse charges it to the value of VDD(Cap) again. This average charging current in the VDD(Cap) supply can be measured and will be proportional to the total capacitance on the output of the pseudo-inverter, the power supply value and the frequency, through the expression, lavg=C*VDD(Cap)*F, where F is the frequency of the periodic waveforms. The V1 and V2 pulses must not overlap so no current flows from the power supply to ground during the transitions. If several measurements of lavg (average charging current) are made at different power supply values for a fixed frequency and lavg is plotted against the power supply value, then the slope of the straight line result is CF. Dividing CF by the frequency yields the total capacitance. This value however, includes not only the cross-over capacitance desired but the capacitance of the driving stub and the drain capacitances of the transistors. In order to separate one from the other, a second pseudo-inverter is fashioned identical in layout to the first except the M2 line is missing. Capacitance of this reference structure is determined in the same manner as the test structure. The difference of the two capacitances is the cross-over capacitance desired.
The implementation of the test structure requires 6 pins for test such as VDD(Cap), VDD(NoCap), VSS, NWELL, V1 and V2. However, probe pad sizes and spacing are huge relative to the area required to implement the pseudo-inverters and interconnect structure, so this is a tremendous waste of silicon area. Large silicon area is very costly even for test chip work.
There have been efforts to reduce the number of required pins and minimize the silicon area. V1 and V2 can drive several test structures and reference structures in parallel and the reference structure with VDD(No Cap) can be common to several test structures, since it is not necessary to have one reference structure per test structure. For example, one of the conventional wafer probe pad patterns may be a 2×12 array including 2 columns×12 rows of probe pads. Assuming 24 probe pads, only 19 test structures may be able to be tested with a single 2×12 probe pad array since a total of 24 pins (including 19 pins for VDD_CAPs, a pin for VDD_NOCAP, and 4 pins for V1, V2, NWELL and VSS) are supported. With the growth of available metal layers on silicon, the number of test structures needed to fully characterize the metal system may be approximately 480. In other words, 26 of 2×12 probe pad arrays are required to fully characterize the metal system, assuming that 19 test structures are supported per 2×12 probe array. In such case, the silicon area required for all these probe pads is still excessively large. If the number of the test structures is limited to reduce the silicon area less than a prescribed or assigned area, the test chip may result in incomplete characterization.
Therefore, it would be desirable to provide a system for measuring capacitance with a minimum number of probe pad arrays which represent the total minimum area to accommodate the full set of required test structures.